1. Field of the Invention
The present invention relates to a bus arbiter and a bus arbitrating method, and more particularly, to a bus arbiter and a bus arbitrating method, by which a bus grant signal is preferentially assigned to a bus master that generates a bus request signal causing a page hit.
2. Description of the Related Art
Typically, a bus arbiter performs bus arbitration between a plurality of bus masters connected to a bus. Each of the plurality of bus masters outputs a bus request signal to the bus arbiter. The bus request signal comprises information for requesting access to the bus.
The bus arbiter receives bus request signals, each of which is generated by each of the plurality of bus masters, and outputs a bus grant signal to each of the plurality of bus masters according to a predetermined order. The bus grant signal comprises information for granting access to the bus.
A conventional bus arbiter performs bus arbitration according to a fixed priority scheme and a fairness scheme including, for example, round-robin scheduling. According to the fixed priority scheme, the bus arbiter pre-emptively assigns different priorities to the plurality of bus masters and outputs a bus grant signal to a bus master having the highest priority. The priority assigned to each of the plurality of bus masters is set to a specific value.
Round-robin scheduling comprises selecting all elements included in one group according to a rational order and a predetermined notion of fairness, where each element is sequentially selected from a list from top to bottom. The selection is repeated after returning to the top of the list. In other words, round-robin scheduling pertains to taking turns.
Thus, in a bus arbiter using round-robin scheduling, each bus master uses a bus according to a rational order. As a result, even when a certain bus master needs to preferentially access a bus, the bus master cannot access the bus until its turn in the round-robin schedule.
In a bus arbiter using the fixed priority scheme, a bus master having a low priority may not access a bus. That is, it is difficult to change hardware of the bus arbiter.
As a consequence, the bus arbiter using the fixed priority scheme and fairness scheme, including round-robin scheduling, cannot reduce a memory access latency. Memory access latency has a significant influence upon the performance of a system on chip (SOC).
Therefore, a need exists for a system and method fur reducing memory access latency to improve the performance of a SOC semiconductor.